1. Field of the Invention
The present invention generally relates to a push-pull digital driver circuit, and more particularly to a bipolar driver with feedback to eliminate simultaneously input saturation and output leakage.
2. Description of the Prior Art
Push-pull digital driver circuits are well known and widely used in the digital electronics art. The following patents are examples of prior art circuits.
U.S. Pat. No. 4,347,446, entitled "Emitter Coupled Logic Circuit With Active Pull-Down", discloses a emitter coupled logic gate incorporating an active pull-down transistor in the pull-down circuit with bias connections for the pull-down transistor including components in the differential input circuit of the gate so that the pull-down transistor is active only during a HIGH-to-LOW transition of the output logic signal.
U.S. Pat. No. 4,490,631, entitled "Totem Pole/Open Collector Selectable Output Circuit", discloses a Schottky driver in which the output circuitry is pin selectable totem pole or open collector configuration. Means for reduced propagation delay are present along with means for reducing totem pole current spikes and overall current drain.
U.S. Pat. No. 4,506,176, entitled "Comparator Circuit", discloses a comparator circuit which compares an input voltage signal with a referenced voltage in order to produce a logical signal at the output of the circuit.
U.S. Pat. No. 4,376,900, entitled "High Speed, Non-Saturating, Bipolar Transistor Logic Circuit", discloses a bipolar transistor logic circuit comprising an input terminal for receiving digital logic signals, an output terminal, an output driver including a current sink transistor and a current source transistor, and a control stage coupled between the input terminal and the output driver.
U.S. Pat. No. 4,874,970, entitled "ECL Output With Darlington or Common Collector-Common Emitter Drive", discloses an output drive circuit having an input circuit comprising a differentially coupled pair of transistors. The output of the differentially paired transistors is provided to a pair of output driver transistors connected in a Darlington or a common collector-common emitter configuration which provides an output pull-up signal to an output pin of the integrated circuit containing the described output driver. The opposite output of the differentially coupled pair is provided to a circuit which provides a pull-down pulse to quickly shut off the transistor pair during the high-to-low transition of the output driver transistor.
U.S. Pat. No. 4,476,403, entitled "Low-Level Logic to High-Level Logic Translator Having Improved High State Drive", discloses a Level Converter circuit, converting from a low-level logic voltage to a high-level logic signal using TTL circuit topology.
Two problems common to prior art circuits are input saturation and output leakage. The present invention can be understood most readily with reference to the prior art push-pull digital driver circuit shown in FIG. 1. In this prior art push-pull bipolar driver, complimentary inputs may be coupled to the bases of bipolar NPN switching transistors TA2 and TA3 via the input nodes PA2 and PA3, respectively. It will be appreciated that this circuit is also suitable for operation with a single input signal coupled to node PA3. In this case, node PA2 is coupled to a fixed reference potential. In either case, the collector of TA3 (node COT) is coupled to the base of an upper output transistor pair TT1 and TT2 and the collector of TA2 (node COC) is coupled to the base of a lower output transistor pair TB1/TB2. A positive potential VCC is connected to terminal 10 and a negative potential VEE is connected to terminal 12. Transistor 17 whose base is coupled to a voltage VX provides a constant current source for TA2 and TA3, and transistor 14 in combination with voltage divider 16 regulates the COT node potential when TA3 is on. Transistor TLS level shifts the signal at node COC and transistor 18 provides a constant current to transistor TLS when TLS is on. Transistor 22 establishes the down level of output terminal P51.
As will be appreciated by those skilled in the art, the degree of saturation of transistor TA3 is a function of the forward bias of the junction between input node PA3 (TA3 base) and node COT (TA3 collector). With output node P51 at its down level (-0.5V), node COT should be pulled down low enough to shut off completely the top output transistor pair TT1-TT2. To insure complete turn-off of the top output transistor pair, the base-collector junction (PA3-COT) of transistor TA3 must be heavily forward biased. But the input capacitance after saturation increases exponentially with increasing forward bias. The saturation capacitance, and hence the switching delay for the driver, is difficult to model and therefore predict. Input saturation of a driver that introduces unpredictable delay to the previous stage can cause system failure.
The problem of saturation can be avoided by limiting the forward bias of the transistor to a value below the saturation region. However, in prior art drivers of the type illustrated in FIG. 1, raising the voltage at collector node COT to reduce the forward bias of transistor TA3 in order to reduce saturation, increases the leakage through output transistor pair TA1-TA2 in an exponential manner. Thus, it will be appreciated that input saturation and output leakage are distinct but inter-related problems with prior art push-pull drivers.